Phase-locked loops (PLLs) are traditionally mixed-signal circuits that play a critical role in clock generation and distribution within SoCs. However, as such systems migrate to more deeply scaled process technologies which are unfriendly towards analog/mixed-signal design, designers have turned to all-digital PLL (ADPLL) designs for their stability over PVT variations, compatibility with automated digital design flows, portability between technologies, and dynamic programmability. In this work, we present an ADPLL design in the ASAP7 7 nm predictive technology suitable for digital clock generation and capable of achieving low jitter or fine output frequency resolution through programming of a modular third-order delta-sigma modulator (DSM) for dithering. Schematic- and system-level test benches verify the operation of the ADPLL over a wide range of operating conditions, with measurements at the nominal supply of 0.7 V showing minimum peak-to-peak jitter and output resolution of 5 ps and 9 MHz, respectively, and a coarse frequency tuning range of 0.499-7.239 GHz, all in a projected die area of 1600 μm2 with total power consumption of 2.3 mW.
Digital Frequency-locked Loop Design Strategies in the ASAP7 Open PDK (PDF)